1. Field of the Invention
The present invention relates generally to biasing circuits and methods and, more particularly, to biasing circuits for use in integrated circuits which contain both bipolar and field effect transistors.
2. Background Art
Biasing circuits are used in integrated circuits for determining internal voltage and current levels at various points in the integrated circuit. Exemplary biasing circuits are disclosed in Bipolar and MOS Analog Circuit Desion, Alan B. Grebene, 1984, pages 169-212 and 276-277. Typically, it is desirable that the voltage and current levels remain constant despite variations in temperature, processing and power supply voltages.
FIG. 1A shows a conventional integrated biasing circuit utilizing bipolar transistors. A reference NPN transistor 10 is provided which has its base and collector electrodes connected in common to the output of a current source 12. The emitter electrode of transistor 10 is connected to the circuit common (or the integrated circuit negative supply.)
Current source 12 provides a collector current I.sub.B to transistor 10 which results in a certain base-emitter voltage V.sub.c at node 14. Voltage V.sub.c is a biasing voltage that can be used to bias other exemplary integrated circuit elements, including transistors 16 and 18. Transistors 16 and 18 have their base electrodes connected in common with the base electrode of reference transistor 10 and their emitter electrodes connected in common with the emitter electrode of transistor 10.
Assuming that the base-emitter junction areas of transistors 10, 16 and 18 are the same, the collector currents I.sub.B, I.sub.C1 and I.sub.C2 will be approximately equal. This approximation ignores the effects of base current and the differences in collector voltages of the three transistors.
The FIG. 1A circuit is commonly referred to as a current mirror, since the collector current I.sub.B in transistor 10 is "mirrored" in the collectors of transistor, 16 and 18.
The base-emitter voltages of transistors 10, 16 and 18 are equal so that the current densities of the three transistors will also be maintained approximately equal. The currents in transistors 16 and 18 can be adjusted by varying the emitter-base junction areas of the transistors, as is well known. If, for example, the emitter-base junction area of transistor 16 were twice that of transistor 10, the collector current of transistor 16 would be approximately one-half that of transistor 10.
FIG. 1B is a diagram of a further exemplary conventional biasing circuit which utilizes N channel metal oxide semiconductor (NMOS) transistors rather than the bipolar NPN transistors of the circuit of FIG. 1A. The FIG. 2B biasing circuit includes a reference NMOS transistor 20 having a source electrode connected to the circuit common. The gate electrode of transistor 20 is connected to the drain electrode and to a current source 12.
Current source 12 provides a current I.sub.B to transistor 20 which causes the transistor to produce a certain gate-source voltage V.sub.C at node 22. Voltage V.sub.C is a biasing voltage which can then be used to bias the gate-sources electrodes of transistors, such as transistors 24 and 26.
Assuming that transistors 24 and 26 have the same geometry (W and L) as reference transistor 20, the current conducted by those transistors, I.sub.C1 and I.sub.C2, respectively, will be equal to current I.sub.B.
The biasing circuits of FIGS. 1A and 1B posses at least two serious shortcomings. First, voltage V.sub.C varies with temperature, which can be undesirable in many applications. Second, the node which carries the biasing voltage is a relatively high impedance node. As a result, the biasing circuit is susceptible to the introduction of noise.
The present invention is directed to a biasing circuit and method which produces a bias voltage which is relatively stable with temperature. The circuit output is at a low impedance, therefore, the circuit is less susceptible to noise than convention biasing circuits. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Description of the Preferred Embodiment.